Improving the yield and reliability of memory arrays such as static random access memory (SRAM) arrays are among current design challenges of integrated circuits and microprocessors with large on-die caches. Embedded memory may include single-port SRAM, which has one access port for reading and writing operations, or multi-port SRAM that can provide high-speed communications and image processing. The multi-port SRAM is suitable for parallel operation and improves chip performance. High-performance and low-power multi-core processors have multiple CPUs within a die, which leads to the number of memory accesses increases considerably. Thus, the memory access speed becomes a limiting factor. Demand for multi-port SRAM has increased because the multi-port SRAM can be accessed from multiple ports simultaneously.
One prior approach is a dual-port bitcell implementation that includes a 2 poly-track bitcell (similar to 6 transistor bit cell) with jogged diffusion to obtain a desirable beta ratio for cell stability when both word-lines (WL) A and B are on. This results in a wide bitcell 100 of FIG. 1 with a skewed aspect ratio 4:1. However, skewed cells are not desirable as the local interconnect resistance and total WL resistance capacitance (RC) time constant are affected negatively. Jogged diffusions 110, 120, 130, and 140 of n-type diffusion or p-type diffusion layers are a patterning and reliability concern. Two WL in metal 3 (M3) have to be inserted in 2 poly tracks. This results in narrow and resistive M3 WLs. To meet performance requirements, repeaters are needed. Repeaters add additional area overhead and reduce bit density. Further, the 2 WL are adjacent to each other in M3 with no shielding in between. In the event that two adjacent WLs fire, then there is significant cross-coupling between the WLs. This can adversely impact read stability and/or the ability to write to the bitcell. In addition, due to low p-type diffusion layer density, additional filler cells may need to be added periodically. This also reduces the bit density.
For simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the discussion of the described embodiments of the invention. Additionally, elements in the drawing figures are not necessarily drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of embodiments of the present invention. The same reference numerals in different figures denote the same elements, while similar reference numerals may, but do not necessarily, denote similar elements.